The present invention relates to semiconductor integrated circuit (IC) manufacturing and, more particularly to a method of forming an asymmetric field effect transistor (FET) gate electrode for a memory structure such as a dynamic random access memory (DRAM) structure.
In the field of semiconductor device manufacturing, merged logic DRAM devices are becoming increasingly important. This is so since the coupling of logic devices with DRAM cells provides a device which has all the benefits of DRAMs, but having the speed of conventional logic devices to improve bandwidth and performance.
In such applications, the channel length of the DRAM transfer gate devices continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for low leakage DRAM transfer devices. There is thus a need for novel integration schemes with only limited shrinking of the channel length.
As the DRAM cell size decreases, the transfer gate has consequently shrunk with it. Earlier cell sizes ( greater than 8F2) allow for wiggled gates to keep the array transistor off leakage to a minimum. With the onset of 8F2 cells with equal lines and spaces at minimum feature size, F, in the wordline direction, there is need to provide larger transfer gate lengths of the array pass transistor by non-lithographic techniques. Conventional scaling techniques use shallow junctions (limited by surface leakage and charge writeback characteristics), high channel doping concentrations or halo implants which increase leakage and are thus not easy to incorporate in DRAM processing.
One known process is based on the BEST (BuriEd Strap) cell modified for 8F2. Once the trench capacitor and shallow trench isolation are formed, the gate conductor stack is put down. Typically, the gate conductor stack consists of polysilicon and WSix capped with SiN. During the gate mask opening step, the SiN is patterned and the etch typically stops in the WSix, the resist is stripped and the remaining gate conductor stack is etched with the SiN as a hard mask. Post gate sidewall oxidation, the SiN spacers are formed, followed by a barrier SiN film and boron phosphorus silicate glass (BPSG) deposition, densification and planarization. A TEOS (tetraethylorthosilicate) layer is formed for the damascene bitlines and the bitline contacts are etched borderless to the gates prior to forming the bitline wiring layer (generally tungsten).
Additionally, it is known that the present processing of DRAM structures in the array portion of the device directly links the lithographic dimension to the polysilicon linewidth. Hence, if there is resist webbing, the increase in the polysilicon linewidth is limited, which directly affects the retention of the DRAM cell.
The present invention is thus directed to further improvements in gate conductor processing which can be easily incorporated into existing DRAM processing techniques.
One object of the present invention is to provide a method of manufacturing a gate conductor of a memory device wherein the gate polysilicon can be tailored so as to improve the retention of the DRAM.
Another object of the present invention is to provide a method of manufacturing a gate conductor of a memory device wherein the length of the gate polysilicon can be tailored so as to reduce array off-state leakage.
A yet further object of the present invention is to provide a method of manufacturing a gate conductor which can be easily implemented into existing DRAM processing techniques.
A still further object of the present invention is to provide a method wherein the charge storage characteristics from short channel lengths of the transfer device in the array region is improved.
An even further object of the present invention is to provide a method of manufacturing a merged logic DRAM device that is capable of forming relatively large transfer device gate lengths, without the limitations of gap fill considerations in the array device region, and proximity of the adjacent bordered contact in the support device regions; these considerations are problematic in prior art processing.
A yet further object of the present invention is to provide a method of manufacturing a merged logic DRAM device in which improved reliability of xe2x80x98onxe2x80x99 pitch devices is achieved without being limited by adjacent contacts.
These and other objects and advantages are achieved in the present invention by forming asymmetric gates in which prespacers are utilized in fabricating the same. Specifically, the inventive asymmetric gates are formed utilizing a method which comprises the steps of:
(a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array device regions and support device regions which may have different oxide thicknesses;
(b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer;
(c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon;
(d) forming prespacers on exposed sidewalls of said partially etched gate stack;
(e) completing said mask open etching in said array device regions by etching any exposed polysilicon, while not etching said layer of polysilicon in the support device regions;
(f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array device regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support device regions;
(g) selectively removing said prespacers in said array and support device regions of said structure so as to provide patterned gate conductors, wherein said patterned gates in said array device regions include polysilicon step segments on each side thereof;
(h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support device regions;
(i) selectively trimming some of the polysilicon step segments provided in step (g) so as to obtain one or more patterned asymmetrical gates in said array device region, wherein each asymmetrical gate comprises a first edge having a substantially vertical sidewall extending to said gate oxide layer and a second edge having said polysilicon step segment; and
(j) performing a second oxidization step on said structure so as to form oxide layers having variable thicknesses.
It should be noted that it is preferred in the present invention that the edges of the patterned gate conductors containing the substantially vertical sidewalls face each other so that a borderless bitline contact can be formed in that region of the structure.
In one embodiment of the present invention, a barrier layer is formed between the layer of polysilicon and conductor material layer. When a barrier layer is present, it may be optionally removed during one of the above mentioned etching steps, i.e., steps (c) or (e).
In another embodiment of the present invention, the structure in step (a) above further comprises core circuit device regions which are located between the array device regions and the support device regions. When a core circuit device region is present in the structure, both sides of the patterned gate conductors present therein will include a polysilicon step segment.
In accordance with another aspect of the present invention, an asymmetric field effect transistor (FET) is provided in which a first edge of said FET has a substantially vertical sidewall and a second edge has a polysilicon step segment.
A further aspect of the present invention relates to a memory device structure which includes:
an array device region, said array device region having one or more asymmetric gates, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment; and
a support device region, said support device region including one or more patterned gate conductors, wherein each patterned gate conductor includes edges having substantially vertical sidewalls.
Alternatively, the inventive structure may also include a core circuit device region located between the array device region and the support device region, said core circuit device region comprising one or more patterned gates, each patterned gate including a polysilicon step segment on each side of the gate.
It is noted that the asymmetric gates are provided in the present invention by utilizing the above mentioned prespacers. The use of the prespacers provides a FET which has reduced leakage current when turned xe2x80x98offxe2x80x99, yet the FET is capable of producing a adequate on-current. Thus, the on-current relative to the total off-state current is increased.
The use of the prespacers increases the channel length while moving the source/drain diffusion implants farther away from the conduction channel. This has a favorable effect in that the distance in dopant profile between channel and source/drain is less abrupt, thereby reducing the electric field at this junction, which in turn reduces leakage current.
The core circuits (wordline drivers, sense amplifiers, row decoders, etc) which are adjacent to the array device regions benefit from having the polysilicon step segments on both sides of the gate because the gates are laid out at a tight pitch. Use of the prespacers permits the required channel length for these transistors to be obtained, while the pitch between gate conductors is reduced. Reducing the pitch of these gate conductors helps match the gate conductors up better with the bitlines and wordlines which are wired to them from the array device region.